Bipolar ram cell and process

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357 36, 357 44, 365154, H01L 2972, G11C 1100

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active

046564950

ABSTRACT:
An integrated bipolar RAM cell and process for its manufacture is disclosed. The RAM cell includes first and second cross-coupled bipolar transistors with first and second load elements coupled to the collectors of the first and second transistors, respectively. The load elements can be, for example, diode clamped resistors or lateral PNP transistors. The load elements include regions which are capable of injecting minority carriers into the collectors of the first and second transistors. To avoid charge storage problems and associated reduced switching speed while maintaining high voltage noise immunity, the charge injecting regions are fabricated having an integrated impurity doping less than or equal to about 1.times.10.sup.13 cm.sup.-2.

REFERENCES:
patent: 4045248 (1977-08-01), Shannon et al.
IBM Technical Disclosure Bulletin vol. 24, #1A, Jun. 1981, pp. 85-87 by Denis et al.
Sakai et al., "A 3-ns 1K-Bit RAM Using Super Self-Aligned Process Technology" Oct., 1981, IEEE Journal of Solid State Circuits, vol. SC-16, No. 5, pp. 424-429.
Inadachi et al., "A 6ns 4Kb Bipolar RAM Using Switched Load Resistor Memory Cell" 1979, IEEE Internat'l Solid State Circuit Conference, pp. 108-109.
Hotta et al., "A High-Speed Low Power 4096 x 1 Bit Bipolar RAM", Journal of Solid State Circuits, vol. SC-13, No. 5 Oct., 1978, pp. 651-655.
Toyoda et al., "A 15ns 16Kb ECL RAM with a PNP Load Cell" IEEE International Solid State Circuits Conference, Feb. 1983, pp. 108-109.
Kato et al., "A 16ns 16K Bipolar RAM" IEEE Internat'l Solid State Circuits Conference, Feb. 1983, pp. 106-107.
Toyoda et al., "A High Speed 16 Kbit ECL RAM" IEEE Journal of Solid St. Circuits, vol. SC-18, No. 5, pp. 509-514.

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