Bipolar process using selective silicon deposition

Details Bipolar process using selective silicon deposition Bipolar process using selective silicon deposition

1990-01-02

1991-01-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 89, 437151, 437162, 437233, 437150, 437 27, 148DIG123, 148DIG124, 148DIG9, H01L 21265

Patent

active

049886320

ABSTRACT:
A process is disclosed for fabricating bipolar transistors having self aligned and closely spaced polycrystalline silicon base and emitter electrodes. The process is especially amenable to integration with the fabrication of MOS transistors to form BiMOS integrated circuits. In accordance with one embodiment of the invention, a P type polycrystalline silicon layer is deposited overlying an N type silicon substrate. The polycrystalline silicon layer is patterned to form base contact electrodes and to leave exposed a portion of the surface of the N-type substrate. An electrically insulating layer is formed overlying the polycrystalline silicon base contacts and the exposed silicon substrate. Sidewall spacers are formed on the electrically insulating layer at the sidewalls of the base contact electrode. After etching the electrically insulating material which is not protected by the sidewall spacers, polycrystalline silicon is deposited on the exposed surface of the N type substrate by a process of selective deposition to form an emitter contact electrode. Ion implantation is then used to form an active base and emitter beneath the emitter contact electrode. Dopant impurities are diffused from the base contact electrode into the underlaying silicon substrate to form an extrinsic base region. The sidewall spacers are removed to expose the surface of the silicon substrate which lies between the intrinsic and extinsic base regions. P type dopant impurities are implanting into this exposed region to form a linking base connecting the intrinsic and extrinsic base regions.

REFERENCES:
patent: 4072975 (1978-02-01), Ishitani
patent: 4464825 (1984-08-01), Ports
patent: 4495010 (1985-01-01), Kranzer
patent: 4547231 (1985-10-01), Hine
patent: 4717677 (1988-01-01), McLaughlin et al.
patent: 4786615 (1988-11-01), Liaw
patent: 4879255 (1989-11-01), Deguchi et al.
patent: 4908324 (1990-03-01), Nihira et al.
patent: 4910170 (1990-03-01), Motozima et al.
patent: 4948745 (1990-08-01), Pfiester
Furumura et al., "Selective Growth of Polysilicon", J. Electrochem. Soc.: Solid-State Science and Tech., Feb. 86, vol. 133, #2, pp. 379-383.
Mieno et al., "Selective Doped Polysilicon Growth", J. Electrochem. Soc.: Solid-State Science and Tech., Nov. 1987, vol. 134, #11, pp. 2862-2867.
J. Middelhoer et al., "Polycrystalline Silicon as a Diffusion Source and Interconnect Layer in 1.sup.2 L Realizations", IEEE J. of Solid-State Circuits, vol. 5c-12, #2, Apr. 77, pp. 135-138.

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