Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Reexamination Certificate
1994-12-07
2001-04-24
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
C327S108000, C327S112000
Reexamination Certificate
active
06222414
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an output stage for an integrated power amplifier particularly suited for audio amplifiers.
BACKGROUND OF THE INVENTION
The output stages of power amplifiers are normally designed for maximizing the dynamic excursion of the output voltage (output voltage swing), by reducing as much as possible voltage drops due to the series resistance of the active components (transistors) that form the output stage. There is an ample specific bibliography out of which the volume “Power Integrated Circuit”, published by Mc.Graw Hill, in 1986, pages 9.28-9.35 may be cited.
A widely used technique in power output stages is that of realizing a “bootstrap” line, using for this purpose a relatively large capacitance, that may be externally connected to the IC pins, in order to obtain the maximum peak-to-peak variation of the output voltage. Unfortunately, this technique conflicts with a general IC design trend of eliminating or reducing the need of passive external components to a minimum.
The known configurations of a power output stage are amply reported in literature and substantially are those employing a pair of transistors operating in phase opposition, namely an NPN/NPN, PNP/NPN, pMOS
MOS and nMOS
MOS pair. Of course, the selection of one of the above configurations depends on the fabrication technology that is employed, which determines also the maximum reverse voltage that can be withstood by the devices (for example the maximum VCE of bipolar junction transistors or the maximum VDS of MOS transistors).
Bipolar NPN transistors notably suffer from the problem connected to the so-called “secondary breakdown” phenomenon. Also bipolar PNP transistors are affected by this phenomenon but in a lesser measure than NPN transistors.
On the contrary, DMOS transistors are notably exempt from this problem.
In a mixed technology fabrication process (BJT, CMOS and DMOS) or BCD process, the power MOS transistors that can be realized in a compatible manner with the other type of integrated structures, have internal resistance characteristics that typically show the following values:
(n-channel) DMOS: Ron=0.5 &OHgr;×mm
2
(p-channel) DMOS: Ron=2.2 &OHgr;×mm
2
In particular, the solution of using a complementary pair of DMOS output transistors would appear an ideal choice, by considering also the advantage represented by the fact that the two output transistors would not need a driving current, being intrinsically voltage-controlled devices. However, a p-channel DMOS transistor requires an integration area that may be four times the integration area of an n-channel, complementary DMOS transistor, for the same Ron. Therefore the solution that employs a complementary pair of DMOS transistors is adopted only in a limited number of applications, where the relatively large silicon area requirement is not a problem.
On the other hand, the use of a (more compact) pair of transistors of the same polarity (that is noncomplementary), for example a pair of n-channel DMOS transistors, besides losing a portion equivalent to a VGS voltage of the maximum voltage swing of the output signal or otherwise requiring a bootstrap line, requires also a somewhat more complex driving circuit than the circuit that would be necessary for driving, in phase opposition, a complementary pair of output transistors.
There is a long felt need or utility of a complementary output stage with good breakdown characteristics that would not need externally connected bootstrap components and require a relatively large area of integration.
SUMMARY OF THE INVENTION
It has been found that in a normal BCD fabrication process it is possible to realize a bipolar PNP power transistor, having an internal resistance Ron of about 0.3 &OHgr;×mm
2
, which can be satisfactorily used as the high side part of a complementary output power stage that employs as its low side part, an n-channel field effect transistor.
A so configured output stage is perfectly complementary and therefore does not reduce the output dynamics by a VGS (or by a VBE) and may be driven by a relatively simple stage.
The output stage has an intrinsically high voltage swing characteristic and does not need externally connected boostrap components. The use of power transistors of different technology (a bipolar transistor of the high side or pull-up part and a field effect transistor for the low side or push-down part), permits to reach an outstandingly good compromise between the extent of silicon area necessary for integrating the two power transistors, by exploiting the relatively small size of an n-channel DMOS structure and of a vertical, isolated collector, PNP structure and the driving power requisite, which is required only by the active pull-up element constituted by the bipolar PNP transistor.
According to an alternative embodiment of the output stage of the invention, the pull-up power element, constituted by a bipolar PNP transistor, is driven by a stage composed of a field effect transistor, for example a p-channel MOS transistor, of sufficient size to provide the driving power required by the bipolar output transistor.
According to an embodiment of the invention, the PNP transistor may be constituted by a complex structure that comprises the PNP and NPN transistors, the electrical behavior of which can be equated to that of an equivalent PNP transistor. This solution permits to further reduce the integration area, being the power NPN structure of the PNP equivalent complex structure capable of operating at a higher current density than a PNP structure and therefore requiring a reduced area of integration. Of course, in this latter case, the output voltage swing would be reduced by a VBE but this could be advantageously traded-off with a maximized saving of silicon area.
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“Power Losses of the Cascode
Cini Carlo
Stefani Fabrizio
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
SGS--Thomson Microelectronics S.r.l.
Wells Kenneth B.
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