Bipolar-MOS circuits with dimensions scaled to enhance performan

Details Bipolar-MOS circuits with dimensions scaled to enhance performan Bipolar-MOS circuits with dimensions scaled to enhance performan

1993-01-21

1994-07-26

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3074821, H03K 1901

Patent

active

053329333

ABSTRACT:
An optimum ratio relating the characteristic dimensions of the MOS pull-up and the MOS pull-down devices of a logic circuit with one or more bipolar devices connected to an output of the circuit. This optimum ratio substantially minimizes the propagation delay of the circuit. The first preferred embodiment is shown in a BiNMOS circuit, and the second preferred embodiment is shown in a BiCMOS circuit.

REFERENCES:
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patent: 4703203 (1987-10-01), Gallup et al.
patent: 4837462 (1989-06-01), Watanabe et al.
patent: 4985645 (1991-01-01), Tsutsui
patent: 5049765 (1991-09-01), Young et al.
patent: 5083048 (1992-01-01), Kashimura
Prasad, Raje; "Design and Scaling of BiCMOS Circuits", Proceedings of International Conference on Computer Design (1992): pp. 234-238.
Prasad, Raje et al., "A New Methodology for Design of BiCMOS Gates and Comparison with CMOS", IEEE Transactions on Electron Devices, vol. 39, No. 2, Feb. 1992.

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