Bipolar junction transistor and fabricating method

Details Bipolar junction transistor and fabricating method Bipolar junction transistor and fabricating method

2002-06-05

2004-07-06

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With base region having specified doping concentration...

C257S197000, C257S552000, C257S198000

Reexamination Certificate

active

06759731

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a bipolar junction transistor (BJT) and its fabricating method, and more particularly, to a self-aligned BJT and a self-aligned method for producing the same.
2. Description of the Prior Art
A bipolar junction transistor (BJT) utilizes two type of carriers, “electrons” and “hot holes”, to transmit current. The BJT continues to be a basic circuit element in integrated circuits due to its high switching capability and current carrying capacity. However, the electrons/holes mobility of a silicon BJT, which has a silicon substrate, is lower and not suitable for being applied in high frequency devices. Therefore, the silicon BJT has been replaced with a GaAs BJT, which has a GaAs substrate, or a SiGe hetero-junction bipolar transistor (HBT) in recently semiconductor processes.
Please refer to
FIG. 1
to
FIG. 5
, which are schematic diagrams illustrating a conventional method for forming a silicon BJT. As shown in
FIG. 1
, the silicon BJT is formed on a P-type single crystal silicon substrate
10
including a heavily doped N type (N
+
) region
12
and heavily doped P type (P
+
) regions
14
formed on the substrate
10
. First, an N-epitaxial layer
16
is thermally grown on the substrate
10
, which has a thickness of about 1.2 micrometers (&mgr;m). During formation of the epitaxial layer
16
, dopants of the N
+
region
12
and the P
+
region
14
diffuse upward into the epitaxial layer
16
. Then, a silicon dioxide layer
18
and a silicon nitride layer
20
are formed on the epitaxial layer
16
, respectively. A photolithographic and etching process is performed to remove a portion of the silicon nitride layer
20
, the silicon dioxide layer
18
and the epitaxial layer
16
to expose a portion of the epitaxial layer
16
, thus forming a plurality of openings
22
in the silicon nitride layer
20
, the silicon dioxide layer
18
, and the epitaxial layer
16
.
As shown in
FIG. 2
, a thermal growth process is performed to oxidize the exposed epitaxial layer
16
to an oxide layer
24
, which fills in the opening
22
, with a top surface of the oxide layer
24
being approximately equal to a top surface of silicon dioxide layer
18
. After that, the remained silicon nitride layer
24
is removed. During thermal growth of the oxide layer
24
, the dopants of the N
+
region
12
and the P
+
region
14
are diffused further upward to broaden the N
+
region
12
and P
+
region
14
. Afterwards, a photoresist layer
26
is deposited on the oxide layer
24
, and the photoresist layer
26
is exposed and developed to form an opening
27
in the photoresist layer
26
. Then,suitable N-type dopants, such as phosphorus (P), are ionimplanted through the opening
27
to form an N
+
collector region
28
within the epitaxial layer
16
and beneath the oxide layer
24
.
As shown in
FIG. 3
, the remnant photoresist layer
26
is removed and another patterned photoresist layer (not shown in
FIG. 3
) is formed on the oxide layer
24
. A wet etching process or a reactive ion etching (RIE) process is performed to remove a portion of the oxide layer
24
above the epitaxial layer
16
, thus forming an opening
30
in the oxide layer
24
. Then, a P-polysilicon layer
32
and a silicon dioxide layer
34
are formed on the substrate
10
, respectively. Typically, the polysilicon layer
32
has a thickness of about 8000 angstroms (Å), and the silicon dioxide layer
34
has a thickness of about 5000 to 6000 Å. A patterned photoresist layer (not shown in
FIG. 3
) is formed on the silicon oxide layer
34
, and a photolithographic and etching process is performed to remove a portion of the silicon dioxide layer
34
and the polysilicon layer
32
to form an opening
36
in the silicon dioxide layer
34
and the polysilicon layer
32
, and a portion of the epitaxial layer
16
is exposed.
As shown in
FIG. 4
, a silicon dioxide layer
38
is thermally grown on the substrate
10
that covers a bottom and a sidewall of the opening
36
uniformly. Typically, the silicon dioxide layer
38
has a thickness of between 0.2 to 0.4 &mgr;m. During formation of the silicon dioxide layer
38
, P-type dopants of the polysilicon layer
32
diffuse downwards into the N-epitaxial layer
16
to form P-extrinsic base regions
40
within the epitaxial layer
16
. Then, a directional RIE process is performed to remove a portion of the silicon dioxide layer
38
in the bottom of the opening
36
and on the oxide layer
24
. Further, a relatively low-energy, high-dose ion implantation is performed to form an N shallow emitter region
42
within the epitaxial layer
16
, which has a thickness of about 0.2 &mgr; by implanting the arsenic (As) ions through the opening
36
into the epitaxial layer
16
. Similarly, a relatively high-energy, high-dose ion implantation is performed to form an N
+
raised subcollector
44
, which has a thickness of about 0.2 micrometers, by implanting phosphorus (P) ions through the opening
36
into the epitaxial layer
16
. The energy and heat cycling conditions for the phosphorus implantation are selected such that the bottom of the raised subcollector
44
nominally submerges into the N
+
region
12
. And a relatively middle-energy, low-dose boron ion implantation is performed to form an intrinsic base region
46
beneath the shallow emitter region
42
and above the raised subcollector
44
, by implanting the As ions through the opening
36
into the epitaxial layer
16
.
Finally, as shown in
FIG. 5
, a photolithographic and etching process is performed to form two contact vias (not shown in
FIG. 5
) on the polysilicon layer
32
and the collector region
28
. Then, a metal layer is filled in the contact vias and the opening
36
to form three metal contacts
50
,
52
, and
48
, and the conventional BJT is completed.
As stated above, the conventional method for forming the BJT is very complicated. Although the intrinsic base region
46
and the emitter region
42
of the BJT are formed by the self-aligned method, the extrinsic base regions
40
are formed by the thermal diffusion process. So that the contact area between the intrinsic base region, the extrinsic base region and the collector region cannot be controlled precisely. Thus causing higher capacitance between the base region and the collector region and the conventional BJT is not suitable for being applied in high frequency devices. In addition, the interference of the PN junction of the BJT is clearer, the performance of the device is better. However while the SiGe HBT can function in high temperatures, the interference between the SiGe epitaxial layer and silicon of the SiGe HBT will generate a plurality of intersectional arrangements and thus destroy the its high speed characteristic. For this reason, the temperature for forming the SiGe epitaxial layer has to be controlled to be below 700° C. But the conventional BJT has to utilize the thermal diffusion process many times, and therefore the conventional method is not suitable for forming the HBT.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a method for forming a PN junction of a self-aligned bipolar junction transistor (BJT).
It is another object of the claimed invention to provide a self-aligned hetero-junction bipolar transistor (HBT), which is suitable for being applied in high frequency devices.
According to the claimed invention, abipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned e

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