Bipolar dynamic memory cell

Details Bipolar dynamic memory cell Bipolar dynamic memory cell

1979-10-22

1982-01-05

Munson, Gene M.

357 51, 357 92, H01L 2704, H01L 2702

Patent

active

043097162

ABSTRACT:
This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.

REFERENCES:
patent: 3423255 (1969-01-01), Joyce
patent: 3729719 (1973-04-01), Wiedmann
patent: 3861968 (1975-01-01), Magdo et al.
patent: 3938176 (1976-02-01), Sloan
patent: 3982266 (1976-09-01), Matzen et al.
patent: 3998673 (1976-12-01), Chow
patent: 4084174 (1978-04-01), Crippen et al.
patent: 4190466 (1980-02-01), Bhattacharyya et al.
Jambotkar, "Realization of Large-Value Capacitance Across Base and Collector Terminals of a Bipolar Transistor", IBM Tech. Disclosure Bulletin, vol. 21 (8/78), pp. 1004-1006.

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