Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – Plural non-isolated transistor structures in same structure
Reexamination Certificate
2001-12-06
2004-10-12
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
Plural non-isolated transistor structures in same structure
C257S583000, C257S586000
Reexamination Certificate
active
06803642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to a bipolar device having a recessed and raised extrinsic base, and a method for making such a device.
2. Description of the Related Art
Bipolar transistors are three-region, two-junction devices. A typical bipolar transistor is fabricated by sequentially forming on a substrate, a collector layer or region, a base layer or region, and an emitter layer or region. An emitter electrode is formed on the emitter layer. A base electrode is formed on the base layer, on the same side of the substrate and adjacent to the emitter electrode.
Electrically, bipolar transistors can be considered as two diodes back to back. A current flows from the emitter region through the base into the collector. When there is no current to the base, the transistor is turned off. When the transistor is on, the current flows. Only a small current is required to turn the base on enough to allow a current to flow through the entire transistor.
Many bipolar circuits are designed with NPN transistors. NPN represents the respective conductivity types of the emitter, base, and collector. Bipolar transistors feature, e.g., fast switching speeds. The speed and performance of a bipolar transistor is governed by a number of factors, including a vertical base dopant film thickness (base width), the base resistance, and the base-collector and base-emitter capacitances.
One factor affecting the speed and performance of a bipolar transistor is the base width. Ideally, the base width is made as small as possible. The thickness of the base film is preferably as thin as possible given the deposition, diffusion, and thermal cycle constraints of a particular technology integration scheme, such as whether CMOS source and drain implants and anneals were performed following the base deposition. Typically, the thickness of the film is considered as a one-dimensional thickness, disposed directly under a center of the emitter of the device. However, an NPN device is better considered as a two-dimensional structure, which from one technological generation to the next, shrinks in a lateral dimension, and the two-dimensional nature becomes more pronounced. In particular, at lateral portions of the emitter which interface to the base, there is located a part of the base-emitter junction which penetrates less deep (ie, is shallow) into the base film. See, for example,
FIG. 14
which shows a substantially planar shallow base-emitter junction
711
,
722
, and see also U.S. Pat. No. 4,985,744 which is incorporated in its entirety herein. Thus, the base width is large at this location. Device performance suffers from the presence of this shallow part because carriers injected therein take a longer time to transit the base of the device. Thus, reduction or elimination of this shallow part of the junction could improve the speed and performance of an NPN device.
Furthermore, it is well known that, during a high injection operation of a bipolar transistor, minority carrier injection is non-uniform across the base-emitter junction. Because the injection of carriers is exponentially related to the potential applied across the base-emitter junction, this potential drop influences the device such that principally the lateral portion of the emitter affects injects carriers. In this state, the center portion of the NPN device is contributing little to the operation of the device and does not in effect inject carriers. Yet, there is still a capacitance associated with the center portion of the device. This capacitance stores charge and, thus, is a capacitive load which must be accommodated by the device, and which makes the device operate more slowly.
SUMMARY OF THE INVENTION
Thus, to enhance performance, it is desirable to have the base-emitter junction configured such that the emitter at lateral portions thereof extends farther into the base (ie, is at a deeper depth in to the base) than at the center portion, such that the deeper portions dominate the injection of carriers and the capacitance of the device, and that the center portion contributes little capacitance. In effect, the device benefits by converting the “slow” part of the junction into a “fast” deeper part.
The base-emitter junction issues described above seem to have received little notice in the past because devices have had relatively wide emitters, where the “slow” part injection is a smaller part of the total. In addition, devices are being biased into higher injection states in order to obtain higher performance and, therefore, the mechanisms described above are becoming more pronounced. Thus, there seems to be a need in the art to provide a bipolar transistor having a modified depth emitter-base junction compared to conventional bipolar devices.
The present invention satisfies this need by providing a base-emitter junction having a non-uniform depth in a bipolar transistor, and a method of making the same.
As embodied and broadly described herein, the present invention is broadly drawn to a bipolar transistor and a method of making the same. The bipolar transistor includes a substrate, and a silicon germanium layer formed by blanket epitaxy on the substrate. A collector layer is also formed on the substrate, and a recessed and raised extrinsic base layer is formed on the silicon germanium layer. An emitter or emitter layer is also formed on the silicon germanium layer, and a junction is created between the emitter or emitter layer and the intrinsic base layer. According to an essential feature of the present invention, the lateral portions of the emitter extend deeper into the base than the central portion of the emitter. In other words, the lateral portion of the emitter has a Depth D
1
while the central portion of the emitter has a depth D
2
which is less than D
1
. Preferably, D
1
is greater than D
2
by a distance in a range from approximately (±10%) two-10 nm. The transistor further includes an emitter contact or electrode formed on the emitter layer, a base contact or electrode formed on the raised extrinsic base layer, and a collector contact or electrode formed on the collector layer.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 4916083 (1990-04-01), Monkowski et al.
patent: 4975381 (1990-12-01), Taka et al.
patent: 4985744 (1991-01-01), Spratt et al.
patent: 5017990 (1991-05-01), Chen et al.
patent: 5106767 (1992-04-01), Comfort et al.
patent: 5316957 (1994-05-01), Spratt et al.
patent: 290763 (1988-11-01), None
patent: 5175222 (1993-07-01), None
English Abstract of JP5175222A and EPO290763A1.
Freeman Gregory G.
Rieh Jae-Sung
Abate Joseph P.
Dickey Thomas L
International Business Machines - Corporation
Tran Minhloan
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