Patent
1990-07-17
1992-03-10
James, Andrew J.
357 15, 357 34, 357 36, 357 45, 357 51, H01L 2972, H01L 2702, H01L 2948
Patent
active
050953559
ABSTRACT:
A bipolar RAM comprising a plurality of memory cells formed of cross-coupled bipolar transistors and a peripheral bipolar circuit formed of bipolar transistor, provided with an epitaxial layer which is to be the collector region of the bipolar transistor in the memory cell portion which is thinner and has higher impurity density than the epitaxial layer which is to be the collector region of a bipolar transistor in the peripheral circuit.
REFERENCES:
patent: 3969748 (1976-07-01), Horie et al.
patent: 4047217 (1977-09-01), McCaffrey et al.
patent: 4278987 (1981-07-01), Imaizumi et al.
patent: 4566174 (1986-01-01), Yasuda et al.
IEEE Transactions of Nuclear Science, J. A. Zoutendyk, "Modeling of Single-Event Upset in Bipolar Integrated Circuits", Bol NS-30, No. 6, Dec. 1983, pp. 4540-4545.
Higuchi Tetsuo
Shiomi Toru
Suda Kakutaro
James Andrew J.
Mitsubishi Denki & Kabushiki Kaisha
Ngo Ngan Van
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