Bipolar-CMOS semiconductor memory device

Details Bipolar-CMOS semiconductor memory device Bipolar-CMOS semiconductor memory device

1991-02-08

1992-05-05

Gossage, Glenn

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365190, 365177, 365208, G11C 800

Patent

active

051114356

ABSTRACT:
A semiconductor memory device of the composite type comprising bipolar and MOS transistors includes a memory cell array comprising MOS type memory cells arranged in a matrix manner, plural pairs of bit lines for connecting the MOS type memory cells in a column direction, and a plurality of bipolar transistors provided on the bit lines, respectively wherein the bases thereof are connected to the bit lines and the emitters thereof are commonly connected. This device further includes a constant current source connected to the common junction of the emitters of the plurality of bipolar transistors, and a column select unit for selecting of the MOS type memory cells in the column direction by allowing potentials on the bit lines of a pair to be selected of the plural pairs of bit lines to be different from those on the bit lines of non-selected pairs. In addition, this device includes row select means for selecting the MOS type memory cells in a row direction by allowing potentials on the bases of second bipolar transistors connected to word lines to be selected of a plurality of word lines to be different from those on the basis of the second bipolar transistors connected to non-selected word lines. Thus, a semiconductor memory device with low power dissipation and operable at a high speed is realized.

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