Biphase signal receiver

Details Biphase signal receiver Biphase signal receiver

1984-08-29

1987-01-13

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 95, 375110, 329104, H03D 302

Patent

active

046370374

ABSTRACT:
The illustrated receiver 6, in flip-flops 16A-D, stores four sequential samples of a biphase-L signal A1 and shifts the samples into four shift registers 24A-D. The sampled signals are clocked through their respective shift registers 24A-D by selected phases of multiphase clock .phi..sub.1, .phi..sub.2, .phi..sub.3, .phi..sub.4. Thus, each set of four samples is stationary at some location in their respective shift registers for the same clock cycle. A decoder section 10 responds to a transition between adjacent signal levels at the output of the shift registers 24A-D and to a previously sampled signal level A44. The decoder section 10 generates a control signal A32-D32 indicating the detection of a mid-bit biphase-L signal transition. A second storage means responds to the control signal A32-D32 and stores a shift register 24A-D signal level A19, B20-D20 which occurred subsequent to the detected mid-cell transition. The control signal A 32-D32 also synchronizes a recovered clock signal A14 used to clock recovered data A50 to external circuitry.

REFERENCES:
patent: 3982195 (1976-09-01), Turner
patent: 4260952 (1981-04-01), Thomas
patent: 4317211 (1982-02-01), Quesnell, Jr.
patent: 4513427 (1985-04-01), Borriello et al.

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