Binsorter triangle insertion optimization

Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension

Reexamination Certificate

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Reexamination Certificate

active

06424345

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to rendering techniques for computer graphics, and in particular to a technique for optimizing the rendering process for 3-dimensional (3-D) computer graphics.
BACKGROUND OF THE INVENTION
Rendering is the process of converting data representing geometric models into a format for display as individual pixels in an image on a computer screen.
Referring to
FIG. 1
, a graphics processing and display system
110
is shown. Graphics system
110
includes an geometry source
112
, which generates geometry data in the form of component polygons. In particular, geometry source
112
may comprise an Application Program Interface (API)
114
, such as Direct3-D™, executed on a main microprocessor
116
.
Geometry source
112
generates a series of geometry data sets, each representing a component polygon such as a triangle. Thus, each geometry data set includes x, y, and z coordinates for each of the three triangle vertices taken from a particular viewpoint, as well as diffuse and specular color information (RGB) associated with each triangle vertex. Each geometry data set may also include for each vertex quantities such as a transparency factor (alpha), texture map coordinates, a fog value, and a perspective correction value (W).
The three-dimensional (3-D) geometry data generated by geometry source
112
is transmitted to a multimedia processing system
118
. Multimedia processing system
118
may include a graphics accelerator card or chip separate from main microprocessor
116
, or may comprise a set of multimedia logic located on the same processor chip with main microprocessor
116
.
Multimedia processing system
118
processes the 3-D geometry data to generate data representing a two-dimensional (2-D) point-of-view image by processing the data through a 3-D pipeline. This pipeline takes the data for each triangle, evaluates the geometry data at each of the three vertices, rasterizes the triangle across a set of pixels on the screen, and writes 2-D image data out to the frame buffer
120
.
This 2-D image data is stored in a frame buffer
120
on a video card
122
, from which a display image may be created in a conventional manner on a display system
124
. Display system
124
may be, for example, a personal computer monitor, a virtual reality goggle screen, or some other visual display.
Certain operations consume more memory bandwidth, such as, for example, alpha blending, which is becoming increasingly utilized for computer game graphics. In the alpha blending process, an alpha value, usually an integer between 0 and 255, is used to determine how to blend a new value produced by the 3-D pipeline with a value already stored in the frame buffer
120
, thereby creating the affect of semi-transparency. Therefore, during the alpha blending process, the multimedia processing system must read data produced by the 3-D pipeline of multimedia processing system
118
, retrieve data from the frame buffer
120
, perform a blending operation on the data, and write out a final, computed result back to the frame buffer
120
. These types of operations have increased the demands placed on modern graphics processing and display systems
110
.
Accordingly, there is a need for a method of improving the speed and efficiency of 3-D graphics rendering. Specifically, there is a need for an improved method of processing geometry through the 3-D pipeline and reducing the total bandwidth consumed during the overall process of rendering 3-D geometric data.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for rendering polygons in a computer graphics system is provided in which the computer display is divided into a plurality of subregions, and the rasterization process is performed in a micro framebuffer for each subregion, rather than sending raster data for each triangle directly into the frame buffer. Each polygon undergoes a first stage bounding box intersection test in which a bounding box is formed around the polygon and any subregions which intersect the bounding box are identified as subregions likely to intersect with the polygon. If the number or configuration of intersected subregions exceeds a predetermined threshold requirement, then the polygon undergoes a more precise second stage intersection test to identify which subregions are actually intersected by the polygon. If the number or configuration of intersected subregions is below the threshold requirement, then the control data for the polygon is passed on to each of the subregions identified as likely candidates for intersection.
In one embodiment, the polygons are triangles, and the subregions consist of tiles of 32×32 pixels. When the bounding box intersection test finds that a collection of subregions in a 2×2 array or smaller are likely candidates for intersection, all of the subregions in this array receive control information for the triangle. If the collection of subregions is larger than 2×2, the triangle is considered to be “large” and is sent for a second stage intersection test.


REFERENCES:
patent: 6326964 (2001-12-01), Snyder et al.

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