Binomially-encoded finite state machine

Details Binomially-encoded finite state machine Binomially-encoded finite state machine

1986-06-09

1987-06-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307449, 307468, 307469, 340347DD, 34082591, 364716, H03K 19094

Patent

active

046755560

ABSTRACT:
A finite state machine suitable for MOS fabrication is described. The finite state machine includes a programmed logic array (PLA). The PLA AND plane includes logical inputs and state signal inputs. The state signal inputs are decoded binomially. The state signals are used to activate the AND plane loads, thereby avoiding the necessity of using either a constantly active pull-up or precharge/selective discharge circuitry technique.

REFERENCES:
patent: 4032894 (1977-06-01), Williams
patent: 4208728 (1980-06-01), Blahut et al.
patent: 4233667 (1980-11-01), Devine et al.
patent: 4562426 (1985-12-01), Forney, Jr.
patent: 4584567 (1986-04-01), Kinghorn
Rhyne, Fundamentals of Digital Systems Design, Prentice-Hall, Inc., pub., 1973, pp. 229-235.
O'Hara, Jr., "PLA Multifunction Output Latches, IBM T.D.B., vol. 20, No. 12, May 1978, pp. 5205-5208.
Greenspan, "Multiple Partitioned Programmable Logic Array", IBM T.D.B., vol. 19, No. 5, Oct. 1976, pp. 1780-1781.

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