Binning for semi-custom ASICs

Details Binning for semi-custom ASICs Binning for semi-custom ASICs

2007-07-10

2007-07-10

Everhart, Caridad (Department: 2891)

Semiconductor device manufacturing: process

With measuring or testing

C257SE21525, C716S030000

Reexamination Certificate

active

10704850

ABSTRACT:
A binning method is disclosed for measuring semiconductor devices for certain parameters and placing specific devices into different categories or “bins” according to the measured parameters. Measurable parameters include performance/speed-grading, power consumption, current leakage, and the ability to operate at certain temperature extremes. A method for speed grading semi-custom ASIC devices is specifically described that does not require removing partially completed wafers from the fab line for testing. To speed-grade a new boat of partially completed un-customized wafers, a small number of wafers (1 or 2) are processed to completion while being customized specifically for a customer design requiring only the slowest bin. These wafer(s) are then performance tested and the remaining wafers in the boat are certified according to these results for their performance level and placed in a wafer bank for later use.

REFERENCES:
patent: 6060330 (2000-05-01), Huggins et al.
patent: 6817006 (2004-11-01), Wells et al.
patent: 6879032 (2005-04-01), Rosenau et al.

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