BINMOS latch circuit with symmetric set-up times

Details BINMOS latch circuit with symmetric set-up times BINMOS latch circuit with symmetric set-up times

1996-10-15

1998-08-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327198, 327207, H03K 1900, H03K 3286

Patent

active

057962839

ABSTRACT:
A latch circuit comprises a series arrangement of a clock-controlled three-state driver and a clock-controlled latch between a data input and a data output. A bipolar transistor between the driver and the latch has a base connected to driver output, an emitter connected to the latch, and a collector connected to Vcc. A clock controlled and data input controlled discharge path connects the emitter to ground. A clock-controlled feedback path connects the data output to the base of the bipolar transistor. This configuration combines the driving capabilities of BiCMOS circuitry and the transition-independent set-up times of a conventional CMOS latch.

REFERENCES:
patent: 5081377 (1992-01-01), Freyman
patent: 5362998 (1994-11-01), Iwamura et al.

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