Binary word processing method using a high-speed sequential adde

Details Binary word processing method using a high-speed sequential adde Binary word processing method using a high-speed sequential adde

1980-04-10

1982-06-22

Malzahn, David H.

Boots, shoes, and leggings

364786, G06F 750

Patent

active

043366007

ABSTRACT:
The words to be added together by the high-speed sequential adder are stored in shift registers 1.sub.l to 1.sub.p whose serial outputs are connected to the corresponding inputs of a transcoder 2 producing the binary number of "1's" for each bit weight of the words to be added. This value is sent to an adder-divider 4 which adds it to the number of carried "1's" from the immediately lesser weight and divides this sum by 2, sending the fractional part of this half-sum to an output register 5 and the whole-number part to a carry register.
Application: digital filters for PCM telephone switching.

REFERENCES:
patent: 3636334 (1972-01-01), Svoboda
patent: 3711692 (1973-01-01), Batcher
patent: 3723715 (1973-03-01), Chen et al.
patent: 3941990 (1976-03-01), Rabasse
Kovvaras et al., "A Digital System of Simultaneous Addition of Several Binary Numbers", IEEE Trans. on Computers, Oct. 1968, pp. 992-997.
Cukrer et al., "Multiple Input Serial Adder Using Counter", IBM Tech. Disclosure Bulletin, vol. 19, No. 11, Apr. 1977, pp. 4215-4216.

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