Binary voltage-differential sensing circuits, and sense/refresh

Details Binary voltage-differential sensing circuits, and sense/refresh Binary voltage-differential sensing circuits, and sense/refresh

1975-03-05

1977-01-18

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

340173FF, 340173CA, G11C 706, G11C 1124

Patent

active

040042847

ABSTRACT:
In one example, a generally conventional flip-flop circuit is used, including a pair of input field-effect transistors having their gates connected respectively to a pair of circuit nodes A and B. During a preset portion of the cycle, both nodes A and B are preset to an initial reference potential V.sub.R, set so that the transistors turn partially ON and act as variable resistors. Thereafter, an unknown voltage V.sub.X to be sensed is connected to node A, V.sub.X being equal to V.sub.R .+-. .DELTA.V. The flip flop then responds to differential conductivity between the transistors, to produce a binary output voltage at one of two levels set by the sense of .DELTA.V, plus or minus.
In a semiconductor RAM circuit, selected memory cell capacitors are connected in sequence to node A, and the flip-flop circuit senses the cell charge and produces an amplified output representative thereof, which is later fed back to the memory cell to refresh the charge originally stored therein.

REFERENCES:
patent: 3760381 (1973-09-01), Yao
patent: 3774176 (1973-11-01), Stein et al.
patent: 3838404 (1974-09-01), Heeren
patent: 3868656 (1975-02-01), Stein et al.
patent: 3892984 (1975-07-01), Stein
Kraft et al., Low-Power Gated FET Latch, IBM Technical Disclosure Bulletin, vol. 15, No. 7, Dec. 1972, p. 2280.

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