Binary two's complement arithmetic circuit

Details Binary two's complement arithmetic circuit Binary two's complement arithmetic circuit

1992-11-17

1994-07-26

Malzahn, David H.

Boots, shoes, and leggings

36471501, G06F 750

Patent

active

053331206

ABSTRACT:
A negation circuit (28) generates a two's complement negation by inverting only those bits of an incoming number which have a level of significance greater than the significance level at which a transition bit resides. The transition bit and all bits of the incoming number having a significance level less than the transition bit are reproduced at the output (32) of the negation circuit (28). The transition bit is the least significant bit in the incoming number to exhibit a logic one. A negation selector circuit (40) selectively overrides the negation so that a negation is generated only when a select negation signal (34) is active. When a transition detected input signal (38) is active, all bits of the incoming number are inverted- A transition detected output signal (36) provides a signal which activates to indicate that the circuit (28) has detected a transition bit. The negation circuit (28) may be coupled to an adder (66) to form a direct subtractor or a direct adder/subtractor (64).

REFERENCES:
patent: 3816734 (1974-06-01), Brendzel
patent: 3975624 (1976-08-01), Kay
patent: 3976866 (1976-08-01), Motegi et al.
patent: 4707800 (1987-11-01), Montrone et al.

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