Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-06-29
2002-02-26
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S168000
Reexamination Certificate
active
06351429
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention generally relates to binary to binary-encoded-ternary decoding. More specifically, the invention relates to the use of such decoding for the purpose of accessing memory cells.
The quest to increase the density of Dynamic Random Access Memory (DRAM) arrays has produced an array cell layout featuring a 6F
2
cell, as shown in FIG.
1
. The dark circles at the intersections, or crosspoints, of the word-lines and bit-lines represent memory cells. The dashed boxes labeled
1
and
2
highlight the repeating pattern of memory cells in the directions of the word-lines and bit-lines respectively. The word-lines within this unit of periodicity have been labeled A, B and C. Thus, during a memory array access, the multiplexer (MUX) control must select a unique pair of bit-lines dependent upon the A, B, C position of the activated word-line. In particular, at position A, bit-lines X and Z are selected; at position B, bit-lines X and Y are selected; and at position C, bit-lines Y and Z are selected.
It is readily apparent that this information is available as the remainder of a divide-by-three operation on the numerical value of the undecoded word-line address. For example, for word-line
0
, the remainder of 0/3 is 0, which corresponds to position A. Similarly, for word-line
7
, the remainder of 7/3 is 1, which corresponds to position B.
FIG. 2
shows prior art examples that utilize this property, in what are referred to as binary to ternary decoders. More accurately, these decoders should be called binary to binary-encoded-ternary (BET) decoders, since they are implemented in two-state logic systems, while true ternary representation requires three state logic.
SUMMARY OF THE INVENTION
An object of this invention is to provide a procedure and associated circuitry, to perform binary to binary-encoded ternary (BET) decoding of an n-bit binary word.
Another object of the present invention is to provide a procedure, and associated circuitry, to perform binary to BET decoding that does not utilize division-by-3.
A further object of this invention is to provide an improved procedure for identifying memory cells to be accessed in a memory device.
These and other objectives are attained with an integrated circuit memory device comprising an arrangement of physical wordlines, WL
0
-WLn, arranged such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, and such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession. The ternary results A, B or C are used to which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline. Preferably, the ternary results A, B and C are respectively encoded by said binary states of said pair of logical row address bits, said binary states being “00,” “01,” and “10” respectively.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.
REFERENCES:
patent: 5287305 (1994-02-01), Yoshida
patent: 5432735 (1995-07-01), Parks et al.
patent: 5841874 (1998-11-01), Kempke et al.
patent: 5920886 (1999-07-01), Feldmeier
patent: 6108227 (2000-08-01), Voelkel
Hsu Louis L.
Netis Dmitry
Ross John M.
International Business Machines Corp.
Le Vu A.
Neff, Esq. Daryl K.
Phung Anh
Scully Scott Murphy & Presser
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