Binary synchronous count and clear bit-slice module

Details Binary synchronous count and clear bit-slice module Binary synchronous count and clear bit-slice module

1984-05-29

1986-11-04

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Particular parallel gating or clock signal

307440, H03K 2340

Patent

active

046213708

ABSTRACT:
A binary synchronous bit-sliced counter comprising a plurality of cascaded identical stages (slices). Each stage only requires for its operation a source of potential V.sub.dd, a carry-in signal input line, a clock signal input line, a reset signal input line and a carry-out signal output line. Cascading of the slices is implemented by connecting the carry-out signal output line of one slice to the carry-in signal input line of another slice and connecting the clock signal and reset signal input lines to all cascaded stages in parallel.

REFERENCES:
patent: 3833822 (1974-09-01), Carbrey
patent: 4360742 (1982-11-01), Freyman
patent: 4366394 (1982-12-01), Clendening et al.
patent: 4464774 (1984-08-01), Jennings
Hayes, John P., "A Survey of Bit-Sliced Computer Design," Advanced Microprocessors, pp. 277-300.
A Survey of Bit-Sliced Computer Design by John P. Hayes, pp. 203-250, vol. 5, Journal of Digital Systems published by Computer Sciences Press, Inc. 1981.

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