Binary signal generating circuit with parallel sample and hold c

Details Binary signal generating circuit with parallel sample and hold c Binary signal generating circuit with parallel sample and hold c

1990-12-04

1991-12-24

Williams, Howard L.

Coded data generation or conversion

Sample and hold

341159, 307353, H03M 136, H03K 523

Patent

active

050756885

ABSTRACT:
A single sampling switch i provided for a plurality of sample/hold function-equipped comparators. Thus, when the sampling switch is turned on, an analog signal is fed to each sample and hold circuit, and when it is turned off, the analog signal fed in at that time is sampled and held in each sample/hold function-equipped comparator. The analog signal values sampled and held in the sample/hold function-equipped comparators are averaged when the averaging switch is turned on. In this manner, since the timing for sampling and holding is controlled by the single sampling switch, a smaller number of switching elements are sufficient and the possibility of the timing for sampling and holding differing between the sample/hold function-equipped comparators is eliminated.

REFERENCES:
patent: 4507649 (1985-03-01), Dingwall et al.
patent: 4539551 (1985-09-01), Fujita et al.
patent: 4547763 (1985-10-01), Flamm
patent: 4612531 (1986-09-01), Dingwall et al.
patent: 4845383 (1989-07-01), Iida
patent: 4903028 (1990-02-01), Fukushima
"A CMOS 40 MHz 8b 105mW Two-Step ADC", by Noriyuki Fukushima et al., ISSCC Digest of Technical Papers, pp. 14-15, Feb. 1989.

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