Binary resistor network and its use for labelling related compon

Details Binary resistor network and its use for labelling related compon Binary resistor network and its use for labelling related compon

1992-10-30

1995-01-10

MacDonald, Allen R.

395 24, G06F 1518

Patent

active

053815165

ABSTRACT:
A binary resistor network is provided for the labelling of related components of binary or binary-converted images and for artificial vision comprising a plurality of peaks each joined by arches forming binary resistors. Each peak is provided with an elementary processor which enables, with the assistance of a central controller, the association of at least one associative function with each of the arches and a binary constraint with one or more peaks, thus making possible to provide for selective processing of data stored at the site of each of the elementary processors. Each arch of the network is equipped with an associative OR function and forms an accelerated Manchester chain, the establishment time of the network through application of local binary constraints thus being thus linear with the number of peaks.

REFERENCES:
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patent: 5038386 (1991-08-01), Li
Mixed-Mode Simulation Tools for Custom VLSI Design R. Salama et al. 16-19 May 1988.
High-Speed CMOS Adder and Multiplier Modules for Digital Signal Processing in a Semicustom Environment J. Kernhof, Jun. 1989.
VLSI Implementation of Moment Invariants for Automated Inspections G. A. Armstrong et al. 11-13 Mar. 1990.
A Neural Net Based Architecture for the Segmentation of Mixed Gray-Level and Binary Pictures Ali Tabatabai; Terry P. Troudet IEEE 1991, Jan. 1991.

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