Binary relative delay line

Details Binary relative delay line Binary relative delay line

1994-05-06

1997-09-09

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327277, 327278, 327284, 327403, H03H 1126

Patent

active

056660790

ABSTRACT:
A binary relative delay line device having two delay lines, each of which delays, during a time interval, an input signal by a substantially equal amount of time. Each delay line requires a settling time before it is selected during a next time interval. A selection and delay determining circuit is coupled to the two delay lines to select one of them to provide an output signal. A clock is coupled to the selection and delay determining circuit to operate the selection and delay determining circuit at a lower frequency than the frequency of the input signal, the lower frequency being chosen so that any selected delay line has settled before it is selected.

REFERENCES:
patent: 4105979 (1978-08-01), Kage
patent: 4330750 (1982-05-01), Mayor
patent: 4337433 (1982-06-01), Yoshimura
patent: 4354124 (1982-10-01), Shima et al.
patent: 4494021 (1985-01-01), Bell et al.
patent: 4626716 (1986-12-01), Miki
patent: 4737670 (1988-04-01), Chan
patent: 4745310 (1988-05-01), Swapp
patent: 4800304 (1989-01-01), Takeuchi
patent: 4845390 (1989-07-01), Chan
patent: 4868522 (1989-09-01), Popat et al.
patent: 4956797 (1990-09-01), Berard
patent: 4958362 (1990-09-01), Nishibe et al.
patent: 4999526 (1991-03-01), Dudley
patent: 5079519 (1992-01-01), Ashby et al.
patent: 5095233 (1992-03-01), Ashby et al.
patent: 5121010 (1992-06-01), Hoshizaki et al.
patent: 5128554 (1992-07-01), Hoshizaki
patent: 5173617 (1992-12-01), Alsup et al.
patent: 5204555 (1993-04-01), Graham et al.
patent: 5216301 (1993-06-01), Gleeson, III et al.
patent: 5218314 (1993-06-01), Efendovich et al.
patent: 5237224 (1993-08-01), Delisle et al.
patent: 5258660 (1993-11-01), Nelson et al.
patent: 5272729 (1993-12-01), Bechade et al.
patent: 5309035 (1994-05-01), Watson, Jr. et al.
patent: 5317202 (1994-05-01), Walzman
patent: 5359232 (1994-10-01), Eiterbeim et al.
patent: 5371416 (1994-12-01), Atriss et al.
patent: 5389830 (1995-02-01), Buckingham et al.
patent: 5394024 (1995-02-01), Buckenmaier et al.
patent: 5550514 (1996-08-01), Liedberg
Transactions on Circuits and Systems--1: Fundamental Theory and Applications, vol. 41, No. 2, Feb. 1994 "A New Method for Clock Distribution".

Affiliated with

Also associated with

Rating

Binary relative delay line does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Binary relative delay line, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Binary relative delay line will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-72562