Binary priority encoder

Details Binary priority encoder Binary priority encoder

2006-06-06

2006-06-06

Nguyen, Linh V. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S159000

Reexamination Certificate

active

07057546

ABSTRACT:
Apparatuses for binary priority encoding are described. A binary priority encoder (100, 100L) includes a data input bus (139), a first logic tree (110) coupled to receive data from the input bus (139), and a second logic tree (130) coupled to receive a portion of the data from the input bus (139). The first logic tree (110) is configured to provide a flag signal (154) indicating whether at least one bit of the data is active. The first logic tree (110) is configured to provide control signals. The second logic tree (130) is coupled to receive the control signals. The second logic tree (130) is configured to select first partial addresses from the portion of the data responsive to the control signals. The control signals are further provided to the second logic tree (130) as second partial addresses.

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