Binary phase accumulator for decimal frequency synthesis

Details Binary phase accumulator for decimal frequency synthesis Binary phase accumulator for decimal frequency synthesis

1992-07-10

1994-12-06

Chin, Stephen

Pulse or digital communications

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331 34, 364762, 455260, 327107, H03D 324

Patent

active

053717651

ABSTRACT:
A direct digital synthesizer of the phase-accumulator type, constructed entirely of binary-radix digital hardware, generates signals with decimally-defined frequency resolution. The synthesizer is supplied with a clock signal which is also decimally-defined. The usual decimal-binary incompatibility problems of such a combination are overcome by the use of a phase accumulator which is partitioned into two segments. The first segment is assigned the most significant portion of the desired frequency, and the other segment is assigned the remaining portion of the desired frequency. The two segments have different arithmetic moduli. Typically, the modulus of the first segment is a power of two, while that of the second segment is an integer other than a power of two. A procedure is given for determining both the point of partition and the second arithmetic modulus.

REFERENCES:
patent: 4816774 (1989-03-01), Martin
patent: 4951004 (1990-08-01), Sheffer et al.
patent: 4984186 (1991-01-01), Maerder
patent: 4992743 (1991-02-01), Sheffer
patent: 5010506 (1991-04-01), Hrncirik
patent: 5034977 (1991-07-01), Chen et al.
Hewlett-Packard Journal, Feb. 1989, "A Generating a Phase-Locked Binary Reference Freguency", p. 68.
Microwaves & RF, Sep. 1991, "Fast Synthesizer." Portion of an artical addressed by the invention, and presuming it would be solver"eventually" by fast versions of the old BCD accumulator technique. p. 122.

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