Binary parallel computing arrangement for additions or subtracti

Details Binary parallel computing arrangement for additions or subtracti Binary parallel computing arrangement for additions or subtracti

1975-06-23

1976-03-30

Dildine, Jr., R. Stephen

Registers

Transfer mechanism

Traveling pawl

G06F 750

Patent

active

039476715

ABSTRACT:
A parallel adder with sequential carry ripple is subdivided into sections. Detector circuits are distributed over the various digit positions of the adder. Each detector circuit receives the digit pairs of the input operands of at least one adder position. The detection circuits indicate the beginning or the end of a carry ripple chain by testing the condition "both input digits zero or both input digits one". Via a coder, the output signals of the detection circuits are combined in the form of group indicating signals, each of which corresponds to a predetermined distance between the digit positions. By means of the group indicating signals a clock circuit is controlled in such a manner that the operating time is limited to the time required for carry rippling.

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