Binary parallel adder employing high speed gating circuitry

Details Binary parallel adder employing high speed gating circuitry Binary parallel adder employing high speed gating circuitry

1974-03-08

1976-01-13

Malzahn, David H.

Registers

Transfer mechanism

Traveling pawl

G06F 750

Patent

active

039327345

ABSTRACT:
In a binary parallel complementing L.S.I. adder, a C-MOS transmission gate is provided in each stage with its input and output directly connected to the carry in and carry out leads of the stage. The gate is switched by complementary control bits derived by stage input logic operating on the bits to be summed, whereby very fast passage of a carry through the stages is achieved. The transmission gate consists of p- and n- channel MOS transistors with their sources connected in common to the input and their drain electrodes likewise connected in common to the output.

REFERENCES:
patent: 3717755 (1973-02-01), Briley
patent: 3743824 (1973-07-01), Smith
patent: 3829713 (1974-08-01), Canning
patent: 3843876 (1974-10-01), Fette et al.

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