Binary or BCD adder with precorrected result

Details Binary or BCD adder with precorrected result Binary or BCD adder with precorrected result

1978-06-16

1979-10-23

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

041722884

ABSTRACT:
An adder provides either binary or binary coded decimal operation under the selection of a control input. The data inputs are a pair of four bit operands and a carry in for providing an additional capability of greater than four bits. Outputs, in addition to the four bit result, include carry propagate and carry generate signals for the four bit group. Binary operation is conventional. For binary coded decimal operation, the adder corrects an initial binary result to the binary coded decimal format by adding six when there is a group carry generate signal present thus forming an intermediate result. This intermediate result is formed before the occurrence of the carry in from a preceding stage. In the final stage of the adder, the intermediate result is incremented to form the final four bit result if there is a carry in.

REFERENCES:
patent: 3089644 (1963-05-01), Wensley
patent: 3486015 (1969-12-01), Asada et al.
patent: 3711693 (1973-01-01), Dahl
patent: 3809872 (1974-05-01), Yamamura et al.
patent: 3813623 (1974-05-01), Namiya et al.
patent: 3935438 (1976-01-01), Grupe
patent: 3991307 (1976-11-01), Peddle et al.
Agrawal, "Fast BCD/Binary Adder/Subtractor", Electronics Letters, vol. 10, No. 8, Apr. 1974, pp. 121-122.
Kolsky, "Adding Technique with Simultaneous Correction & Carry", IBM Tech. Disclosure Bulletin, vol. 7, No. 7, Dec. 1964, p. 591.

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