Binary operator using block select look ahead system which serve

Details Binary operator using block select look ahead system which serve Binary operator using block select look ahead system which serve

1992-05-07

1995-07-18

Malzahr, David M.

Boots, shoes, and leggings

364787, G06F 750

Patent

active

054348102

ABSTRACT:
A binary operator comprises a plurality of carry select adder circuits each including a cumulative carry propagate signal generating means and a cumulative carry generate signal generating means and/or a plurality of block look ahead carry generator circuits each including a cumulative block carry propagate signal and cumulative block carry generate signal generating means and a real carry signal generating means. The carry select adder circuit does not simultaneously generate two presumed sum signals and select and output one of the presumed sum signals, but directly performs operations on a carry propagate signal, a cumulative carry propagate signal and a cumulative carry generate signal which are necessary for generating the presumed sum signal pair and a real carry signal to calculate the real sum signal. The block look ahead carry generator circuit does not simultaneously generate two presumed carry signals and select and output one of the presumed carry signals, but uses a cumulative block carry propagate signal, a cumulative block carry generate signal and a carry signal to directly generate the real carry signal. The number of elements of the binary operator is greatly reduced without sacrificing the high speed of computation since two presumed sum or carry signals are never generated in parallel.

REFERENCES:
patent: 3553446 (1971-10-01), Kruy
patent: 3993891 (1976-11-01), Beck et al.
patent: 4525797 (1985-06-01), Holden
patent: 4559609 (1985-12-01), Robinson, Jr. et al.
patent: 4639888 (1987-01-01), Nussbaecher
patent: 4761760 (1988-08-01), Tomoji
Bedrig, "Carry -Select Adder" IRE Trans. on Electronic Computers Jun., 1962 pp. 340-346 364/788.
Anderson, "Fire-Level Combinations Sum Predict and Carry Propagate Adder" IBM Tech. Disclosure Bulletin vol. 14 No. 1 Jun. 1971 pp. 112-113 364/788.
Hwang, K., "Computer Arithmetic Principles, Architecture, and Design", 1979, pp. 78-91, John Wiley and Sons, New York, U.S.
Vabre, J. P., "La retenue anticipee dans les circuits d'addition", L'Onde Electrique, vol. 61, No. 1, Jan. 1981, pp. 57-64.
Patent Abstracts of Japan, vol. 9, No. 253 (p. 395), Jun. 10, 1985 for JP-A-60 105 041 (Nippon Denki), Jun. 10, 1985.
F. Okamoto et al "High-Speed CMOS Adder with CLA Organization", 1989 Spring National Convention Record, IEICE, p. 5-239, Mar. 1989.
Kai Hwang, Computer Arithmetic: "Principles, Architecture, and Design", John Wiley & Sons, Inc. (1979) pp. 69-96.

Affiliated with

Also associated with

Rating

Binary operator using block select look ahead system which serve does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Binary operator using block select look ahead system which serve, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Binary operator using block select look ahead system which serve will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2421352