Binary multiplier using ternary code

Details Binary multiplier using ternary code Binary multiplier using ternary code

1983-11-18

1986-12-09

Malzahn, David H.

Boots, shoes, and leggings

364760, G06F 752

Patent

active

046284729

ABSTRACT:
The invention provides a high-speed binary multiplier.
The binary digits x.sub.i of the multiplicand X and y.sub.j of the multiplier Y (in two complement form) are converted by respective coders into coefficients a.sub.i and b.sub.j such that

REFERENCES:
patent: 3691359 (1972-09-01), Dell et al.
patent: 3730425 (1973-05-01), Kindell et al.
patent: 4122527 (1978-10-01), Swiatowiec
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4546446 (1985-10-01), Machida
IEEE Transactions on Computers, vol. C.27, No. 3, Mar. 1978 (New York, U.S.A.), P. Corsini et al., "Uniform Shift Multiplication Algorithms without Overflow", pp. 256-258.
K. Hwang: "Computer Arithmetic-Principles, Architecture and Design", 1979, John Wiley & Sons (New York, U.S.A.), pp. 149-151.

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