Boots – shoes – and leggings
Patent
1990-09-06
1992-03-10
Herndon, Heather R.
Boots, shoes, and leggings
364786, G06F 752, G06F 750
Patent
active
050954555
ABSTRACT:
A binary multiplier circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced. A fixed operand is multiplied by a variable operand by storing a partial result of the multiplication using an accumulator and a shift register with the binary calculation circuit. A two-input multiplexer has one of its inputs connected to the output from the register and an output connected to the input of the register. The variable operand is applied serially to a control input of the multiplexer.
REFERENCES:
patent: 4853887 (1989-08-01), Jutand et al.
patent: 4985862 (1991-01-01), Hmida et al.
Duhamel Pierre
Hmida Hedi
ETAT Francais represente par le Ministre Delegue des Postes et
Herndon Heather R.
Nguyen Long T.
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