Binary multiplication cell circuit

Details Binary multiplication cell circuit Binary multiplication cell circuit

1980-09-30

1982-12-07

Smith, Jerry

Boots, shoes, and leggings

307448, 307472, 364786, G06F 752

Patent

active

043631070

ABSTRACT:
A binary multiplication cell circuit suitable for a MOS transistor integrated circuit. The cell circuit has a NOR circuit for obtaining a partial product of one binary digit of a multiplicand and one binary digit of a multiplier and a full adder for obtaining result of multiplication (or augend) and a carry digit based on the partial product, an augend supplied from a given multiplication cell circuit and a carry digit supplied from another given multiplication cell circuit. The full adder comprises two AND circuits, three NOR circuits, an inverter and an exclusive OR circuit. Preferably, the exclusive OR circuit is constituted by an exclusive NOR circuit and an inverter.

REFERENCES:
patent: 3950636 (1976-04-01), Dao
patent: 4293922 (1981-10-01), Davio et al.
Article Nikaido et al., An N-MOS 16-bit Parallel Multiplier, Dentsu Gakkai Gijutsu Kenkyu Hokoku, pp. 48-8 (SSD79-24) Jul. '79.

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