Binary MOS switched-carry parallel adder

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364784, G06F 750

Patent

active

044221576

ABSTRACT:
A fast and inexpensive MOS switched carry parallel full adder is disclosed. Each stage includes only one inverter and two shunting transistors for the carry signal, one transistor being of the depletion type. Each stage further includes two EXCLUSIVE-OR gates and two NOR gates.

REFERENCES:
patent: 3454751 (1969-07-01), Brastins et al.
patent: 3717755 (1973-02-01), Briley
patent: 3843876 (1974-10-01), Fette et al.
patent: 4071905 (1978-01-01), Oguchi et al.

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