Binary MOS ripple-carry parallel adder/subtracter and adder/subt

Details Binary MOS ripple-carry parallel adder/subtracter and adder/subt Binary MOS ripple-carry parallel adder/subtracter and adder/subt

1985-09-24

1987-07-28

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

046835482

ABSTRACT:
The adder/subtracter disclosed sums a plurality of n-digit binary-coded numbers (A, B, C . . . Z) successively by forming corresponding partial sums (Sb, Sc . . . Sz) according to the following recursive formula:

REFERENCES:
patent: 3496345 (1970-02-01), Mitchell
patent: 3535502 (1970-10-01), Clapper
patent: 3602705 (1971-08-01), Cricchi
patent: 3603776 (1971-09-01), Weinberger
patent: 3636334 (1972-01-01), Svoboda
patent: 4229802 (1980-10-01), Eggermont
patent: 4336600 (1982-06-01), Houdard et al.
patent: 4369500 (1983-01-01), Fette
Beraud et al, "High-Speed Accumulator" IBM Tech. Disclosure Bulletin, vol. 17, No. 1, Jun. 1974, pp. 118-119.

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