Binary MOS carry-look-ahead parallel adder

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G06F 750

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active

044647298

ABSTRACT:
Unlike prior art parallel adders, which employ conventional EXCLUSIVE-OR gates, the parallel adder disclosed uses special EXCLUSIVE-NOR gates constructed from only three transistors, so that a considerable space-saving and a reduction of power dissipation are achieved on the integrated-circuit chip. Instead of noninverted digit signals, inverted digit signals are used to form the E and D signals which are combined by means of a complex gate for each binary weight to form the inverted carry signal of this weight. This complex gate includes a number of AND elements equal to the number of the stage, and a NOR element combining the outputs of these AND elements and the D signal of this stage. The inverted carry signal of a stage and the inverted subtotal signal of the next higher-order stage are combined by means of an EXCLUSIVE-NOR gate of the above-mentioned special circuit construction to form the noninverted sum signal of the next higher order stage. The inverted subtotal signal of each stage is also provided by an EXCLUSIVE-NOR gate of the above-mentioned special circuit construction combining the E and D signals of that stage.

REFERENCES:
patent: 3202806 (1965-08-01), Menne
patent: 3681584 (1972-08-01), Wolf
patent: 3728532 (1973-04-01), Pryor
patent: 3925652 (1975-12-01), Miller
patent: 4163211 (1979-07-01), Miura
Schmookler et al., "Group-Carry Generator", IBM Tech. Disclosure Bulletin, vol. 6, No. 1, Jun. 1963, pp. 77-78.

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