Binary magnitude comparator with asynchronous compare operation

Details Binary magnitude comparator with asynchronous compare operation Binary magnitude comparator with asynchronous compare operation

1989-08-07

1991-03-26

Shaw, Dale M.

Communications: electrical

Digital comparator systems

G06F 702

Patent

active

050032860

ABSTRACT:
A binary magnitude comparator having a plurality of rows and a plurality of columns, including a most significant column and a least significant column. The binary magnitude comparator is not clocked and performs a comparison asynchronously in a shorter period of time than a clocked binary magnitude comparator of corresponding bit size. The binary magnitude comparator comprises a plurality of comparator cells forming a plurality of rows and columns. Each row corresponds to a register, and each column a bit position in that register. A comparison is begun by selecting one or more registers with a plurality of select signals coupled to comparator cells in the most significant column, and proceeds from the most significant column, to successively next most significant columns, and terminates when the comparison in the least significant column is complete. The result of the binary magnitude comparison is a first output signal representing a binary value of a highest-valued register, and a second output signal, indicating which row or rows had the highest value. The binary magnitude comparator is designed to operate with an arbitrary number of rows and columns.

REFERENCES:
patent: 3609703 (1971-09-01), Peacock
patent: 4841279 (1989-06-01), Walters, Jr.

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