Binary logic structure employing programmable logic arrays and u

Details Binary logic structure employing programmable logic arrays and u Binary logic structure employing programmable logic arrays and u

1982-06-15

1985-03-12

Zache, Raulfe B.

Boots, shoes, and leggings

307465, 34082583, 364716, G06F 100

Patent

active

045049041

ABSTRACT:
Binary logic structure is described which requires less space on an integrated circuit chip. This structure includes an encode programmable logic array responsive to a first group of binary input signals for producing a smaller number of binary signals which are encoded to identify different binary value combinations for the first group of binary input signals. This structure further includes a decode programmable logic array responsive to a second group of binary input signals and to the encoded binary signals produced by the encode programmable logic array for producing binary output signals representing logical functions of binary input signals in both the first and second groups. The chip space occupied by the encode programmable logic array is less than the additional chip space that would be required if the encode and decode programmable logic arrays were replaced by a single programmable logic array for receiving all the binary input signals in both the first and second groups. When used to provide microword generation apparatus for a microprogrammed digital system, the encode programmable logic array is responsive to a plural-bit system instruction for producing a plural-bit instruction identification signal uniquely representative of such system instruction but having a smaller number of bits than the system instruction. In such case, the decode programmable logic array is responsive to the instruction identification signal and to number signals produced by a sequence counter for producing a sequence of microwords needed to execute the system instruction.

REFERENCES:
patent: 3287286 (1976-10-01), Muehldorf
patent: 3987287 (1976-10-01), Cox et al.
patent: 4034356 (1977-07-01), Howley et al.
patent: 4207556 (1980-06-01), Sugiyama et al.
C. Barre, "La Famille des FPLA", Electronique et Applications Industrielles, Apr. 1978, pp. 21-25.
M. S. Schmookler, "Two-Level Programmed Logic Array Adder", IBM Technical Disclosure Bulletin, Apr. 1979, pp. 4313-4316.
P. W. Cook et al., "A Study in the Use of PLA-Based Macros", IEEE Journal of Solid-State Circuits, Oct. 1979, pp. 833-840.

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