Binary incrementer circuit

Details Binary incrementer circuit Binary incrementer circuit

1975-03-20

1976-11-02

Malzahn, David H.

Registers

Transfer mechanism

Traveling pawl

G06F 750

Patent

active

039899403

ABSTRACT:
An incrementer circuit, wherein a "1" is added to binary input information of n digits to provide binary output information, characterized in that output information of the lowest digit is produced as inverted input information by an inverter circuit, and that output information of each of the second-lowest to nth digits is produced by passing either input information of the particular digit or its inverted signal from an inverter circuit through a corresponding one of transfer gate transistor paths, which are controlled by the information of the digits lower than the particular digit.

REFERENCES:
patent: 3505511 (1970-04-01), Campano et al.
patent: 3603774 (1971-09-01), DeVarda et al.
patent: 3675000 (1972-07-01), Lincoln et al.
patent: 3704361 (1972-11-01), Patterson et al.
W. N. Carroll "High-Speed Counter Requiring No Carry Propagation" IBM Journal Oct. 1960 pp. 423-425.
J. W. Dieffendeufer "No Ripple Counter with Latch Implementation" IBM Tech. Disclosure Bulletin Aug. 1967, pp. 241-245.
J. E. Elliott "Increment-Decrement Logic" IBM Tech. Disclosure Bulletin Aug. 1968 pp. 297-298.

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