Binary division of signed operands

Details Binary division of signed operands Binary division of signed operands

1989-11-15

1991-05-14

Shaw, Dale M.

Boots, shoes, and leggings

G06F 752

Patent

active

050162101

ABSTRACT:
A divider unit (15), having a divider circuit (16) and a divider controller (17), generates signed quotient and signed remainder signals in response to input signed dividend and signed divisor signals. The divider circuit (16) has an adder/subtracter unit (22), a mux (24), a zero/sign detector unit (23), and a shiftable register (28) which are controlled by the divider controller (17) and which cooperate to iteratively generate signed partial remainder and signed partial dividend signals, necessary for the computation of signed quotient and signed remainder signals, using either a restoring or non-restoring binary division algorithm.

REFERENCES:
patent: 4320464 (1982-03-01), Desmonds
patent: 4441158 (1984-04-01), Kanuma
patent: 4503512 (1985-03-01), Doran
patent: 4546447 (1985-10-01), Sawada
patent: 4692891 (1987-09-01), Yamaoka et al.
patent: 4777613 (1988-10-01), Shahan et al.
patent: 4872214 (1989-10-01), Zurawski

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