Binary divider as for a digital auto flesh circuit

Details Binary divider as for a digital auto flesh circuit Binary divider as for a digital auto flesh circuit

1983-11-21

1985-10-29

Masinick, Michael A.

Facsimile and static presentation processing

Static presentation processing

Attribute control

358 21R, 364766, H04N 9535

Patent

active

045503397

ABSTRACT:
A pipelined binary divider which operates at video rates which consists of N like subtraction stages coupled in cascade. Each subtraction stage includes a latch for storing the divisor, the partial quotient and a modified dividend from the previous stage. A binary multiplier is arranged to multiply the latched modified dividend by a factor of two, the result being applied as the minuend to a binary subtractor and to one input of a multiplexer. The latched divisor is applied as the subtrahend to the subtraction circuit. The sign bit from the subtraction circuit controls the multiplexer to selectively pass the multiplied dividend as the dividend to the succeeding stage, for negative differences, or the magnitude of the difference from the subtraction circuit for positive differences. The sign bit is complemented and applied as an additional least significant bit (LSB) to the partial quotient. Each stage adds one bit to the quotient. In the cascade combination of the aforedescribed stages, each stage is performing a partial quotient subtraction for respective ones of N successive quotients, the first stage performing the first subtraction of the (R+N)th quotient and the last stage performing the last subtraction of the Rth quotient.

REFERENCES:
patent: 4381550 (1983-04-01), Baker
An Algorithm for Rapid Binary Division, Wilson and Ledley, IRE Transactions on Electronic Computers, Dec. 1961, pp. 62-70.
An Algorithm for Non-Restoring Division, Sanyal, Computer Design, May 1977, pp. 124-127.
W. Demmer et al., "Pipelining-Verfahren in der Digitalen Signalverarbeitung", Elektronik, 12.2.1982, pp. 73-77.

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