Coded data generation or conversion – Digital code to digital code converters – With error detection or correction
Patent
1992-11-13
1994-05-24
Williams, Howard L.
Coded data generation or conversion
Digital code to digital code converters
With error detection or correction
341156, 341160, H03M 106
Patent
active
053153014
ABSTRACT:
An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.
REFERENCES:
patent: 4912470 (1990-03-01), Hosotani et al.
patent: 4958157 (1990-09-01), Miki et al.
patent: 4982193 (1991-01-01), Saul
patent: 5260706 (1993-11-01), Chung
"Monolithic Expandable 6 Bit 20MHz CMOS/SOS A/D Converter", IEEE Journal of Solid-State Circuits, vol. SC-14, No. 6, pp. 926-931, Dec. 1979, by Andrew G. F. Dingwall.
"An 8-MHz CMOS Subranging 8-Bit A/D Converter", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 6, pp. 1138-1143, Dec. 1985, by Andrew G. F. Dingwall.
Hosotani Shiro
Ito Masao
Miki Takahiro
Mitsubishi Denki & Kabushiki Kaisha
Williams Howard L.
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