Binary controlled digital tapped delay line

Details Binary controlled digital tapped delay line Binary controlled digital tapped delay line

1992-07-23

1994-04-26

Levy, Stuart S.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307605, 307608, 307602, H03K 513

Patent

active

053069714

ABSTRACT:
An electronic, binary-controlled digital tapped delay line is realized by a plurality of like stages connected in cascade. Each stage comprises a differential amplifier circuit responsive to a pair of input signals for producing a pair of output signals and including a differential transistor pair. A first loading circuit formed by a plurality of load devices interconnected to produce a cumulative loading effect is connected to an input of a first transistor of the differential transistor pair for delaying turn-on of the first transistor. Similarly, a second loading circuit formed by a plurality of load devices interconnected to produce a cumulative loading is connected to an input of a second transistor of the differential transistor pair for delaying turn-on of the second transistor, the first and second loading circuits each being connected to a first circuit node. A delay control circuit is responsive to a binary control signal and connected to the first circuit node for causing turn-on of the first and second transistors to be delayed by a set amount of time when the binary control signal is asserted.

REFERENCES:
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Otsuji, Tai.varies.Ichi et al., A 10-ps Resolution, Process-Insensitive Timing Generator IC, IEEE Journal of Solid-State Circuit, vol. 24, No. 5, Oct. 1989, pp. 1412-1417.

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