Binary coded decimal addition

Details Binary coded decimal addition Binary coded decimal addition

2007-11-20

2007-11-20

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10720940

ABSTRACT:
The binary coded decimal (BCD) adder circuit adds two BCD encoded operands, with an input carry bit, and produces a BCD encoded sum. The adder has three stages. The first stage receives two BCD encoded operands as inputs, groups the inputs into contiguous blocks of 4-bits each, computes an intermediate sum vector and carry vector without considering the input carry bit, and also computes propagation and generate functions for each 4-bit group. The second stage is a carry look ahead circuit which computes all carries from the input carry, and the propagate and generate functions of the 4-bit groups from the first stage. The third stage adjusts the intermediate sum vector with pre-correction factors which depend upon the input carry and the carries generated from the second stage and the carry vectors from the first stage.

REFERENCES:
patent: 3629565 (1971-12-01), Schmookler et al.
patent: 3935438 (1976-01-01), Grupe
patent: 4001570 (1977-01-01), Gooding et al.
patent: 4118786 (1978-10-01), Levine et al.
patent: 4138731 (1979-02-01), Kamimoto et al.
patent: 4139894 (1979-02-01), Reitsma
patent: 4172288 (1979-10-01), Anderson
patent: 4559608 (1985-12-01), Young et al.
patent: 4638300 (1987-01-01), Miller
patent: 4707799 (1987-11-01), Ishikawa et al.
patent: 4718033 (1988-01-01), Miller
patent: 4799181 (1989-01-01), Tague et al.
patent: 4805131 (1989-02-01), Adlietta et al.
patent: 4866656 (1989-09-01), Hwang
patent: 5745399 (1998-04-01), Eaton et al.
M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals, (2001), pp. 129-132 and 145-147, second edition, Addison Wesley Longman, New Delhi.
John F. Wakerly, Digital Design, Principles and Practices, pp. 441-443, 2001, third edition, Pearson Education Asia, New Delhi.
Zvi Kohavri, Switching and Finite Automata Theory, pp. 138-144, 1978, second edition, Tata McGraw Hill, New Delhi.

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