Binary code instrumentation to reduce effective memory latency

Details Binary code instrumentation to reduce effective memory latency Binary code instrumentation to reduce effective memory latency

2006-02-27

2010-06-01

Zhen, Wei Y (Department: 2191)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C717S140000, C717S141000, C717S145000, C717S155000, C717S158000, C717S161000

Reexamination Certificate

active

07730470

ABSTRACT:
A system for binary code instrumentation to reduce effective memory latency comprises a processor and memory coupled to the processor. The memory comprises program instructions executable by the processor to implement a code analyzer configured to analyze an instruction stream of compiled code executable at an execution engine to identify, for a given memory reference instruction in the stream that references data at a memory address calculated during an execution of the instruction stream, an earliest point in time during the execution at which sufficient data is available at the execution engine to calculate the memory address. The code analyzer generates an indication of whether the given memory reference instruction is suitable for a prefetch operation based on a difference in time between the earliest point in time and a time at which the given memory reference instruction is executed during the execution.

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