Binary character generator for interlaced CRT display

Communications: electrical – Land vehicle alarms or indicators – Internal alarm or indicator responsive to a condition of the...

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340723, 340733, 340744, G09G 106

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active

046493786

ABSTRACT:
An apparatus for flicker reduction and increased writing speed into image memory in a CRT display having an interlaced scan with masking of low priority symbols. The apparatus expands or duplicates adjacent picture elements to provide redundant illumination for alternate fields, thereby providing at least two adjacent illuminated picture elements proximate to a masking image to reduce flickering during the writing of alternate fields. Writing into a single memory location commands illumination of a plurality of adjacent pixels, thereby reducing image memory writing time. The apparatus utilizes an image memory wherein video bit signals are written into only storage locations whose binary x coordinate has a predetermined first digit, and whose binary y coordinate has a predetermined first digit. Signals in storage locations whose addresses correspond to picture elements P.sub.I,J, P.sub.I-1,J, P.sub.I-1, .sub.J+1, and P.sub.I, J+1 are read from the image memory, and a Boolean OR sum signal is generated therefrom which is converted to an analog signal. The picture element P.sub.I,J is illuminated in response to an analog signal representing the Boolean OR sum signal 1.

REFERENCES:
patent: 4119954 (1978-10-01), Seitz et al.
patent: 4354186 (1982-10-01), Groothuis

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