Binary carry-select adder

Details Binary carry-select adder Binary carry-select adder

1993-04-26

1995-03-07

Envall, Jr., Roy N.

Boots, shoes, and leggings

G06F 750

Patent

active

053964454

ABSTRACT:
The present invention comprises a binary select adder for adding two numbers of N binary bits. where N=2.sup.K +R and K is an integer whereas R is an integer remainder and 0.ltoreq.R<(2.sup.K+1 -2.sup.K). The binary carry select adder comprises a plurality of full adder pairs for adding one bit of the two numbers wherein each of the pairs including a first adder for processing an initial sum and carry assuming a carry select of zero and a second adder for processing an initial sum and carry assuming a carry select of one. The binary carry select adder further includes a plurality of fourplex processing means each connected to the pair of full adders or another one of the fourplex processing means forming a plurality of intermediate stages for receiving four input data and generating a pair of appropriate intermediate `carrys`. The binary carry select adder further includes a plurality of multiplex processing means receiving input from the pairs of full adders or the fourplex processing means, each of the multiplex processing means further receiving a carry from the multiplex processing means of one-less significant bit for generating a final sum output for each bit and a final carry output for the N-th bit. The inter-connected pairs of full adders, fourplex processing means and multiplex processing means forming (K+1) adder cells wherein each cell processing 2.sup.m bits (where m=1,2, . . ,K) of the N bits for generating a sum output for each bit in the adder cell and a carry for input to next adder cell whereas the last adder cell processing last R bits of the N bits.

REFERENCES:
patent: 3316393 (1967-04-01), Ruthazev
patent: 3553446 (1971-01-01), Kvuy
patent: 4764888 (1988-08-01), Holden et al.

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