Binary arithmetic coding device

Coded data generation or conversion – Digital code to digital code converters – To or from code based on probability

Reexamination Certificate

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Details

C341S050000, C341S051000, C341S065000, C341S067000, C341S106000, C375S240020, C375S240120, C375S240140, C375S240250, C382S100000, C382S107000, C382S247000, C382S284000

Reexamination Certificate

active

08072359

ABSTRACT:
An object of the present invention is to provide a binary arithmetic coding device that allows real-time processing with a higher image quality. At a timing at which a ternary data string for a target bit is outputted, an updated coding range width and an updated range width of less probability are outputted. For that reason, while a binary conversion unit (32) and an f value retention processor (33) convert the ternary data string into a binary data string to output a coded bit, a binary arithmetic re-normalization unit (31) is allowed to perform a processing of binary arithmetic coding for the next bit.

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