Binary and n-valued LFSR and LFCSR based scramblers,...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07487194

ABSTRACT:
N-valued with n≧2 scramblers, descramblers, sequence generators and sequence detectors operate with Linear Feedback Shift Registers (LFSRs) in Galois configuration. Detectors and descramblers in Fibonacci configuration relate to generators and scramblers with LFSRs in Galois configuration. The content of a shift register in a sequence detector in Galois configuration is calculated. Binary and n-valued scramblers in Galois configuration are matched with corresponding self-synchronizing descramblers with Linear Forward Connected Shift Registers. Systems, including communication systems apply scramblers and descramblers, sequence generators and sequence detectors in Galois configuration.

REFERENCES:
patent: 4304962 (1981-12-01), Fracassi et al.
patent: 4663501 (1987-05-01), Pospischil
patent: 4669118 (1987-05-01), Pospischil
patent: 5844989 (1998-12-01), Nishida et al.
patent: 5966447 (1999-10-01), Nishida et al.
patent: 6038577 (2000-03-01), Burshtein
patent: 6122376 (2000-09-01), Rao
patent: 6282230 (2001-08-01), Brown et al.
patent: 6295301 (2001-09-01), Asano
patent: 6665692 (2003-12-01), Nieminen
patent: 6788668 (2004-09-01), Shah et al.
patent: 6933862 (2005-08-01), Neff
patent: 6947468 (2005-09-01), Medlock
patent: 2003/0063677 (2003-04-01), Mix et al.
patent: 2004/0090907 (2004-05-01), An
patent: 2007/0047623 (2007-03-01), Eun et al.
patent: 2007/0168406 (2007-07-01), Meyer
Steven A. Tretter, Communication System Design Using DSP Algorithms—Chapter 9 Pseudo-Random Binary Sequences and Data Scramblers, 1995, Springer, pp. 163-171.
Seok et al., Synchronization of Shift Register Generators in Distributed Sample Scramblers, 1994, IEEE transactions on Communications, vol. 42, No. 2/3/4, pp. 1400-1408.
Srini et al., A Parallel SONET Scrambler/Descrambler Architecture, 1993, IEEE, pp. 2011-2014.
Steven S. Gorshe, CRC-16 Polynomials Optimized for Applications Using Self-Synchronous Scramblers, 2002, IEEE, pp. 2791-2795.
Benjamin Arazi, Self Synchronizing Digital Scramblers, Dec. 1977, IEEE trascations on communications, vol. com-25, No. 12, pp. 1505-1507.
Sklar, Bernard “Reed-Solomon Codes”,Downloaded from URL http://www.facweb.iitkgp.ernet.in/˜pallab/mob—com/art—sklar7—reed-solomon.pdf. (unknown), pp. 1-33.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Binary and n-valued LFSR and LFCSR based scramblers,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Binary and n-valued LFSR and LFCSR based scramblers,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Binary and n-valued LFSR and LFCSR based scramblers,... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4092775

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.