Binary and decimal adder unit

Details Binary and decimal adder unit Binary and decimal adder unit

1999-01-21

2001-09-18

Ngo, Chuong Dinh (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06292819

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a binary and decimal adder unit for high speed additions and subtractions of operands having a plurality of binary and decimal digit positions.
BACKGROUND OF THE INVENTION
Several techniques of designing adder units for performing high speed additions of decimal operands consisting of a plurality of decimal digits are disclosed by Schmookler and Weinberger in “High Speed Decimal Addition”, IEEE Transactions on Computers, Volume 20, No. 8, August 1971, pages 862-866. These techniques provide a direct production of decimal sums without the need of first producing the binary sums, and they avoid the decimal correction of the result in an additional operation cycle by adding six to each sum digit where a carry is produced. The techniques use carry generate and propagate functions for the decimal digits to perform a carry look ahead function over the digit positions and for the direct production of the decimal sum digits.
A combined binary/decimal adder unit using a carry look ahead logic through a plurality of decimal digit positions and a direct production of the decimal sum digits is disclosed in the U.S. patent application Ser. No. 969.244, Haller et al, “Combined Binary/Decimal Adder Unit”. In this unit pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.
The time critical path of the add and subtract operations resides in the highest decimal digit position for which the carry-in signal is generated at the end of the carry processing operation. Re-corrections of the sums and differences by −6 corrections would require an additional operation delay which limits cycle rate of the processor unit in which the decimal additions and subtractions have to be performed. The previous unit avoids such additional operation delay but still requires some circuit level delay for the selection of the pre-sum selection.
SUMMARY OF THE INVENTION
It is an object of the invention to further reduce the operation delay of decimal additions and subtractions in a binary and decimal adder unit which uses the generation and selection of pre-sums. Another object is to permit an increased cycle rate of the processor unit in which such binary and decimal adder unit is utilized. Still another object of the invention is to reduce the circuitry and the chip area required for the binary and decimal adder unit. The invention is defined in the claims.
The binary and decimal adder unit according to the invention provides a pre-sum logic which comprises a carry prediction logic for generating decimal digit position carry out signals on the presumption of a zero carry input and of a one carry input into the decimal digit. In response to gating signals derived from the carry out signals of the carry prediction logic and to operation control signals a sum digit pre-selection is performed for selecting a qualified pre-sum digit generated on the presumption of a zero carry input into the decimal digit position, and for selecting a qualified pre-sum generated on the presumption of a one carry input into the decimal digit position. The pre-sum selection logic also comprises a two way selector which is responsive to the digit carry-in signals from the digits carry network for selecting one of the qualified pre- sum digits as the correct sum of each digit position.
The pre-selection is performed for all decimal digit positions in parallel to the generation and distribution of the carries in the digits carry network and anticipates the carry-in of the decimal digit positions. The most time critical selection of the qualified pre-sum digits as correct sum output is performed by means of the carry-in signal into the high order decimal position, and the circuit delay required for this time critical selection is reduced to one multiplexer level.
According to one embodiment of the invention, the sum pre-selection is extended to true and modified pre-sums to reduce the circuitry of generating pre-sums. In the adder unit of this embodiment the operand modification is applied only to one of the operands by selecting one of the operands as true operand, as its complement and as a six incremented version of said one operand while the other operand is supplied in the true form only. A first pre-sum logic circuit is provided for generating a sum of the uncorrected operand and the six incremented operand and a difference of the uncorrected operands in each of the decimal digit positions under the presumption of a zero carry input into the decimal digit position, and a second pre-sum logic circuit is provided for generating a sum of the uncorrected operand and the six incremented operand and a difference of the uncorrected operands in each of the decimal digit positions under the presumption of a one carry input into the decimal digit position. Each of the pre-sum logic circuits is connected to a modification logic which applies a six decrement operation to the pre-sum outputs of the pre- sum logic circuits. The pre-selection logic then selects the unmodified or the decremented pre-sums as qualified pre- sums. This embodiment of the invention reduces the extent of circuitry required for the pre-sum generation and also reduces the chip space required for the binary and decimal adder unit.


REFERENCES:
patent: 5007010 (1991-04-01), Flora
patent: 5146423 (1992-09-01), Fischer et al.
patent: 5745399 (1998-04-01), Eaton et al.
patent: 5928319 (1999-07-01), Haller et al.
Schmookler et al., “High Speed Decimal Addition,” IEEE Transactions on Computers, vol. 20, No. 8, 8/71, pp. 862-868.

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