Binary adder having a fixed operand and parallel-serial binary m

Details Binary adder having a fixed operand and parallel-serial binary m Binary adder having a fixed operand and parallel-serial binary m

1987-09-11

1989-08-01

Harkcom, Gary V.

Boots, shoes, and leggings

364757, 364770, G06F 750, G06F 752

Patent

active

048538876

ABSTRACT:
Binary adder having a fixed operand and a parallel-serial binary multiplier incorporating such an adder. The multiplier comprises a dedicated adder, whose elements (transistors, logic gates, etc.) are wired to incorporate the value of the fixed operand B. The non-fixed operand D is applied in serial form to the control input of a multiplexer. The multiplier also comprises an accumulator-shift register for storing a partial result A of the multiplication. As a function of the state of the multiplexer, the register receives A or A+B.

REFERENCES:
patent: 4153939 (1979-05-01), Kudou
patent: 4417315 (1983-11-01), Russell
patent: 4417316 (1983-11-01), Best
patent: 4584660 (1986-04-01), Young et al.
patent: 4623982 (1986-11-01), Ware
patent: 4700325 (1987-10-01), Ware
IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985, pp. 6450-6453, New York, U.S. "Parallel-Array Incrementing Newtork".
IEEE Journal of Solid-State Circuits, vol. SC-20, No. 2, Apr. 1985, pp. 542-547, IEEE, New York, U.S.; D. A. Henlin et al.: "A 16 Bit.times.16 Bit Pipelined Multiplier Macrocell", FIGS. 2-5.

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