Binary adder circuit with improved inputs

Details Binary adder circuit with improved inputs Binary adder circuit with improved inputs

1988-09-23

1991-01-15

Shaw, Dale M.

Boots, shoes, and leggings

G06F 750

Patent

active

049858629

ABSTRACT:
A binary calculation circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced.

REFERENCES:
patent: 3767906 (1973-10-01), Pryor
patent: 4439835 (1984-03-01), Best et al.
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4831578 (1989-05-01), Bui
"Principles of CMOS VLSI Design" by N. H. E. West and Kamran Eshraghian, published by Addison-Wesley Publishing Company, pp. 317-319.
Proceedings of the IEEE International Conference on Computer Design: VLSI Computers, New York, Oct. 7-10, 1985, "Carry-Save Adders and Their Application for a Multiplication with Factored Multiplicands", by S. Steinlechner et al., pp. 359-362.
Patent Abstracts of Japan. vol. 9, No. 140, Logical Circuit, Masafumi Yamaguchi, Jun. 14, 1985.
International Journal of Mini & Microcomputers, "Bit Serial Techniques in VLSI Parallel Processing", by D. I. Moldovan et al., vol. 7, No. 2, 1985, pp. 49-52.

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